1. Field of the Invention
The present invention relates to a spin transistor with a MOS structure, a programmable logic circuit that includes the spin transistor, and a magnetic memory that utilizes a tunnel magnetoresistive effect, and, more particularly, to a spin transistor that has an amplifying effect and a magnetic memory that can control the recording state through spin injection in the plane direction.
2. Description of the Related Art
In recent years, spin electronics devices that utilize the spin freedom of electrons have been widely developed and studied. Also, more and more studies are being made on application of the tunnel magnetoresistive effect (TMR) to magnetic random access memories (MRAM), magnetic reproducing heads, or the likes. Particularly, attention is being drawn to spin transistors that have semiconductors and magnetic bodies combined.
Typical examples of such spin transistors include a diffusion-type spin transistor (Mark Johnson type; disclosed in M. Johnson et al., Phys. Rev. B37, 5326, (1988)), a Supriyo-Datta spin transistor (spin orbit control type; disclosed in D. Datta et al., Appl. Phys. Lett. 56, 665 (1990)), a spin valve transistor (disclosed in D. J. Monsma et al., Phys. Rev. Lett. 74, 5260 (1995) and K. Mizushima et al., Phys. Rev. B58, 4660 (1998)), a single-electron spin transistor (disclosed in K. Ono et al., J. Phys. Soc. Jpn 66, 1261 (1997)), and a resonant spin transistor (disclosed in N. Akiba et al., Physica B256-258, 561 (1998)).
Also, a spin transistor with a MOS structure that has the source and drain made of magnetic materials, and has a point contact between the channel and the drain, has been developed (disclosed in Japanese Patent Application Laid-Open No. 2003-92412). This point contact is of such a size as to cause a quantum effect for spin-polarized electrons, and has much higher resistance than the channel resistance. The interface resistance between the channel and the drain is the principal factor to determine the magnetization dependency of the drain current. Therefore, with this spin transistor, a higher magneto-resistance ratio (MR ratio) can be obtained.
Also, a programmable logic circuit in which a MRAM and a MOSFET are combined to form basic logic gates such as an AND gate and an OR gate has been developed. In such a programmable logic circuit, the memory state of the MRAM is changed to switch on and off those logic gates.
However, any of the above described spin transistors does not have an amplifying function, and only maintains the switching function among the transistor functions.
The spin transistor disclosed in JP-A No. 2003-92412 has the problem of a decrease in device response speed due to an increase in the resistance of the point contact. Among the reports on experiments carried out on spin transistors having point contacts, there are cases where a high MR ratio was obtained, as well as cases where a high MR ratio was not obtained. It is difficult to apply such spin transistors to a logic circuit that include a number of devices.
In the case of a spin transistor not having a point contact, a high MR ratio can be achieved by employing an intrinsic semiconductor as the semiconductor substrate and magnetic semiconductors as magnetic bodies to be the source and drain. More specifically, a Schottky barrier is formed at the interface between the channel and the source and drain, and spin injection is performed via the Schottky barrier. The magnetic semiconductor can be obtained by replacing part of the atoms of a semiconductor body with a magnetic material such as Mn. However, a magnetic semiconductor cannot presently exhibit a preferable angle ratio at room temperature, and so far has only a limited operability at a low temperature.
Further, when a programmable logic circuit is formed by combining a MRAM and a MOSFET, the wiring structure between a MRAM that is formed with a magnetic layer and a MOSFET that is formed with a semiconductor layer becomes complicated.